interconnect/axi: map from one address space to another - #1522

Here is a case where one would/could use this function.

Thanks @mkuhn99, this is indeed interesting and I understand the need. Please just give me some time to think about it.

This has now been handled with a structured remapping path:

• 39390177c adds src_regions / dst_regions support to AXI and AXI-Lite remappers.
• 2a5ce7859 adds AXI/AXI-Lite regression coverage for region remapping.
• a0dc61851 adds the higher-level SoCBusHandler.add_slave(..., dst_region=...) API.

This allows a LiteX-visible decode region to differ from the downstream/external bus address window, for example:

self.bus.add_slave(
    name       = "ps_io",
    slave      = axi_ps,
    region     = SoCRegion(origin=0x6000_0000, size=0x0030_0000),
    dst_region = SoCRegion(origin=0xe000_0000, size=0x0030_0000),
)

So the Zynq/PS-style remapping use case can now be expressed directly at the SoC bus level, without adding an arbitrary address callback to the low-level AXI connect() helper. The existing strip_origin behavior is kept unchanged as the map-to-zero special case.